The present invention generally relates to logic circuits and semiconductor memory devices having such logic circuits, and more particularly to a logic circuit using a bipolar complementary metal oxide semiconductor (CMOS) gate and a semiconductor memory device using such a logic circuit in a column switch and the like thereof.
Conventionally, there is a random access memory (RAM) using bipolar CMOS gates which have bipolar transistors and MOS transistors within basic gates. In such a RAM, the bipolar transistor having a large driving capacity is used as an output stage transistor of the bipolar CMOS gate which is used in a driver and the like, while the MOS transistor is used for a switch.
FIG. 1A shows an example of output stage npn transistors Tr1 and Tr2. In FIG. 1A, V.sub.CC and V.sub.EE denote first and second power source voltages. Input signals to bases of the transistors Tr1 and Tr2 are obtained from a node N.sub.1 between an emitter of the transistor Tr1 and a collector of the transistor Tr2. The first power source voltage V.sub.CC is applied to a collector of the transistor Tr1 and the second power source voltage V.sub.EE is applied to an emitter of the transistor Tr2, and these power source voltages V.sub.CC and V.sub.EE are similarly applied to MOS transistors constituting a CMOS inverter within the RAM. For example, V.sub.CC =0 V and V.sub.EE =-5.2 V.
An output voltage which is obtained from the node N.sub.1 between the transistors Tr1 and Tr2 which operate with the power source voltages V.sub.CC and V.sub.EE has a high level on the order of -0.5 V which is approximately 0.5 V lower than the first power source voltage V.sub.CC and a low level on the order of -4.7 V which is approximately 0.5 V higher than the second power source voltage V.sub.EE as shown in FIG. 1B. In order to realize a high gate speed of an inverter and the like, it is desirable that a threshold voltage V.sub.TH of a p-channel MOS transistor be low and approximately 0.6 V or less.
On the other hand, a CMOS inverter shown in FIG. 2 within the RAM is also applied with an input signal having a high level on the order of -0.5 V and a low level on the order of -4.7 V. In FIG. 2, the CMOS inverter has a p-channel MOS transistor Qa and an n-channel MOS transistor Qb, and an output is obtained from a node N.sub.2 between the MOS transistors Qa and Qb. When a high-level signal having a voltage of -0.5 V is applied to the CMOS inverter, the n-channel MOS transistor Qb is completely turned ON while the p-channel MOS transistor Qa is unlikely to be completely turned OFF because the first power source voltage V.sub.CC is 0 V and the p-channel MOS transistor Qa has no marginal voltage.
In addition, when the power source voltage gradually reaches a steady level, the rise time and fall time of the signal outputted from the bipolar CMOS gate become large. As a result, because the CMOS inverter supplied with the output signal of the bipolar CMOS gate is provided within a sense amplifier selection circuit, a column switch and the like, a first sense amplifier coupled to a data line and a second sense amplifier coupled to another data line may both be selected at one time when the selection should actually change from the first sense amplifier to the second sense amplifier. In other words, an erroneous operation occurs in the RAM.
Therefore, there is a demand for a logic circuit having a bipolar CMOS gate and a p-channel MOS transistor driven through the bipolar CMOS gate, wherein a marginal voltage of the p-channel MOS transistor is improved so as to guarantee a turning OFF of the p-channel MOS transistor.